This invention relates to an automatic design technique of a semiconductor integrated circuit, and in particular, relates to a technique for automatically positioning external terminals on a surface of a semiconductor chip having pads.
Recently, with the development of high-density and multi-functional semiconductor integrated circuits, the number of pads of a semiconductor integrated circuit and the number of external terminals (i.e., electrode pins) of the semiconductor package tend to increase. Therefore, the design work for determining the positions of the electrode pins and for wiring the electrode pins and the pads becomes complicated. Thus, there is an increasing demand for an automatic design technique.
In automatically positioning the electrode pins and wiring the electrode pins and the pads, it is preferable that the wire length can be short and the single-layer wiring can be used.
Conventional techniques for automatically wiring the electrode pins and the pads are disclosed in Japanese Laid-Open Patent Publication No. 2000-35986 (referred to as Patent Publication 1) and Japanese Laid-Open Patent Publication No. 2000-100955 (referred to as Patent Publication 2).
In Patent Publication 1, a region of a semiconductor chip on which the electrode pins are disposed is divided into four trapezoidal sections. The electrode pins of each trapezoidal region are connected to the pads disposed on a corresponding perimeter facing the trapezoidal region, in accordance with the predetermined order of priority (see paragraphs 0111 through 0120, FIGS. 6 through 9 and FIG. 12 of Patent Publication 1).
In Patent Publication 2, a common lead pattern is used for connecting a plurality of pads and a plurality of electrode pins. The automatic wiring is accomplished by placing the common lead pattern on a suitable position.
However, the techniques disclosed in Patent Publications 1 and 2 have following problems.
In the technique disclosed in Patent Publication 1, the number of the electrodes pins of each trapezoidal region needs to be the same as the number of the pads of the corresponding perimeter. Therefore, if the number of the pads varies from one perimeter to another, it becomes difficult to properly perform the wiring. As a result, many constraints are imposed on the design of the semiconductor integrated circuit.
In the technique disclosed in Patent Publication 2, the total number of the pads and the electrode pins needs to be an integral multiple of the wirings of the lead pattern, and therefore many constraints are imposed on the design of the semiconductor integrated circuit.